During the formation of a semiconductor device such as memory devices, logic devices, microprocessors, etc., several photolithography steps are typically required. Each photolithography step includes the formation of a blanket photoresist (resist) layer, exposing portions of the resist layer to light using a mask or reticle, removing the exposed resist portions (or the unexposed resist portions if negative resist is used), etching the underlying layer using the resist as a pattern, then stripping the resist.
Many layers, for example some oxides and metals, have a highly polished surface which reflects light back to the photoresist and exposes the resist in unwanted areas. This unintentionally exposed portion of the photoresist is removed (or remains, in the case of negative resist) and results in less than desirable patterning of the underlying layer. One method used to decrease reflected light is through the use of dielectric antireflective coatings (DARC layers), which are well known in the art of photolithography. A DARC layer is formed as a blanket layer, typically from silicon-rich oxide or oxynitride using chemical vapor deposition (CVD), over the layer to be etched. The blanket resist layer is formed over the DARC layer, then exposed to a pattern of light projected through a reticle. The exposed portion of the resist (or the unexposed portion, if a negative resist is used) is removed. Next, the DARC layer and the underlying layer are etched using the resist as a pattern. After patterning the DARC layer and the underlying layer, both the resist and DARC layers are typically removed. The resist is removed using an ash step comprising exposure of the resist to an oxygen plasma, then DARC layer is removed, typically using a wet etch but also in some processes using a dry etch.
One problem which can result from the use of DARC layers occurs from the removal of the layer. The DARC layer is typically exposed to a wet etch of SuperQ (3% phosphoric acid, H3PO4, 37% ammonium fluoride, NH4F) or QEtch II (1% H3PO4, 39% NH4F). This wet etch also enters the opening in the underlying layer, and may etch this layer and expand the opening in the underlying layer beyond that etched with the photoresist pattern. This expansion may also occur if the DARC layer is removed with a dry etch. In many device designs this will undesirably expose another conductive feature, which may lead to shorting when the opening is filled with a conductive layer which contacts the exposed feature. This is especially true as semiconductor engineers design devices with tight critical dimensions (CD's) to maximize feature density. This may result in an unreliable device or a nonfunctional device, thereby decreasing yields and increasing costs. While the DARC layer is nonconductive, leaving it in place can contribute to device leakage.
A process which results in the aforementioned shorting of device features is depicted in FIGS. 1-5. FIG. 1 depicts a conventional structure comprising a semiconductor wafer 10 having doped regions therein 12, shallow trench isolation (STI) 14, transistors comprising gate oxide 16, control gate 18, for example polysilicon, conductive enhancement layer 20, for example tungsten silicide, capping layer 22, and dielectric spacers 24. FIG. 1 further depicts conductive pads 25, dielectric base layer 26, for example borophosphosilicate glass (BPSG), storage capacitors comprising capacitor bottom plate 28, cell dielectric 30, and capacitor top plate layer 32. FIG. 1 further depicts a second dielectric layer 34 comprising BPSG or tetraethyl orthosilicate (TEOS), an antireflective coating (ARC) 36, for example manufactured from silicon-rich oxide or oxynitride, and a patterned photoresist layer 38. During the exposure of photoresist layer 38 during photolithography, antireflective layer 36 decreases the reflection of light from the surface of dielectric layer 34 back into resist layer 38. The structure of FIG. 1 is easily manufactured by one of ordinary skill in the art from the information herein. Other structures may be formed during the manufacture of the structure of FIG. 1 which are not depicted for ease of explanation.
After forming the FIG. 1 structure, an etch is performed using the photoresist layer 38 as a pattern to remove portions of ARC layer 36, dielectric 34, and base dielectric 26 to expose conductive pad 25. This forms the digit line contact opening 40 as depicted in FIG. 2.
After etching the digit line contact opening 40, resist layer 38 is removed, for example using an ash step (i.e. exposing the layer to an oxygen plasma) followed by a clean using a dilute solution of hydrogen peroxide (H2O2) and sulfuric acid (H2SO4) to remove any remaining residue to result in the FIG. 3 structure. Next, the ARC layer is removed, for example by exposing the ARC layer to a wet etch comprising SuperQ or QEtch II, which also exposes the base dielectric 26 and conductive pad 25 to the wet etch. During removal of the ARC layer, the base dielectric layer 26 may also be etched which results in the structure of FIG. 4. In FIG. 4, the capacitor storage plate 28 is exposed which will result in shorting of the storage plate 28 with a plug layer 50 formed within contact opening 40 as depicted in FIG. 5.
A new method and structure which reduces or eliminates the problems resulting from removing an antireflective layer with a wet or dry etch would be desirable.